It goes up in the same time when HLD_CYC goes down at the end of the instruction. When this signal goes down (at the beginning of PHI1) the current cycle is finished and the next one in order starts at the beginning of the next PHI2 phase. One is HLD_CYC which tells the timing logic that current cycle signal should be held. There are two other signals which controll the instruction cycle timing. Cycle (CYC_M1, CYC_R1, etc.) and state (T1, T2, etc.) are changing their value at the beginning of PHI2.

Their use is shown below.ДЇigure 3 - basic cycle (CYC_M1, CYC_R1) and state (T1, T2, T3, T4) signalsДЄs it can be seen from the Figure 3 and Table 1 all timing signals are one phase ahead. Instruction timing ROM and cycle signals Instruction timing ROMДЄll output signals are explained there. The exception is INS_DI_EI and INS_HLT because those instructions don't need registers or ALU.ДЈ. Only 46 signals are routed to other decoding ROMs where signals for ALU or register file are created. There is no signal for NOP instruction as it doesn't require any particular action.ДЄll 48 signals are routed to the instruction timing ROM where is the most of the informations for creating timing signals like CYC_M1 or T1. If there is need to distinguish a particular instruction within the group it is done in logic elsewhere. The order of the signals is the same as in the real chip.ДЄll 18 input signals are decoded in 48 groups of instructions. In the schematic above is only a part of the ROM. Those two signals are used in instruction decode ROM to distinguish instructions with register argument (A, B, C, D, E, H, L) and memory argument (M pseudoregister). From the table above it is clear that this happens in cycle M1, state T3 and phase PHI1, exactly when opcode fetch ends.ДЄdditional signals passed thru PHI2 are delayed by some halfphase and thus their changes are aligned with T3 - see figure 2 where transition from instruction 3E (MVI A,xx) to instruction 21 (LXI H,xxyy) is shown. So as we have seen above - the instruction register is loaded from the data bus when signals CYC_M1, T3 and PHI1 are high. All those cycles are one phase ahead of real machine cycles and states so that the logic has time to settle down before any action is triggered.ДЇollowing table explains it better (HLD_CYC and NXT_INS signals will be explained later):ДЄll logical values were sampled at the falling edge of corresponding PHI1 or PHI2 signal.

Many parts of the chip are controlled by basic timing signals for cycle identification (CYC_M1, CYC_R1, CYC_R2, CYC_W1 and CYC_W2) and for state identification (T1, T2, T3, T4, T5 and T6). Loading is triggered by signal INS_LOAD which is high when CYC_M1, T3 and PHI1 signals are high.

Those signals are and instruction register is loaded from data bus. Additional 9 signals (first 3 shown) are created via PHI2. The output signals not shown here are INS_B3, /INS_B3. Instruction register and decode ROM Instruction registerДЇigure 2 - INS_B* signals going from instruction register Then it is postponed to the next PHI2 phase (so it is in phase with CLK (OUT)), amplified and goes out to the pad RESET OUT.Дў. It is postponed until next PHI1 phase and routed as signal RESET throughall the chip. The signal is conditioned by inverting Schmitt trigger. So CLK (OUT) is in phase with PHI2 but has different duty cycle.Д¬hanges in /RESET IN signal are recognized during PHI2 phase. PHI1 is then negated and amplified and goes out to the pad CLK (OUT). The signal from the oscillator is divided by 2 and then goes thru flip-flop which makes the non overlapping clock signals PHI1 and PHI2 which synchronize everything in the chip. X1 and X2 pads are connected to the Pierce oscillator. Note the yellow strips (PHI1 active) and cyan strips (PHI2 active). Intel 8085 Partial Schematic Intel 8085 partial schematic

Intel 8085 processor